A semiconductor device may use a voltage of 3.3V or less as a power-supply voltage, to minimize power consumption and maximize reliability. However, the semiconductor device may be connected to other peripheral devices in a single system. Since a peripheral device may use a voltage of 5V or more as the power-supply, a semiconductor device may include a high-voltage element for supporting a high input voltage received from an external part.
A high-voltage element may have the same structure as that of a MOS element (i.e., a low-voltage element), and may be simultaneously integrated with a low-voltage element according to a predetermined fabrication process. A related method for manufacturing the semiconductor device including the high-voltage element will hereinafter be described in detail.
Impurities may be implanted using an ion implantation process to form a high-voltage (HV) N-well and a high-voltage (HV) P-well, a low-voltage (LV) N-well, and a low-voltage (LV) P-well in a semiconductor substrate. Impurities may be implanted using an ion implantation process to form a N-drift area and a P-drift area over the high-voltage P- and N-wells contained in the surface of semiconductor substrate.
A shallow trench isolation (STI) mask for exposing a shallow trench isolation (STI) area on the semiconductor substrate may be formed according to a LOCOS process. Ion-implantation may be used to form a channel stop. Field oxide layers may be formed in the STI layer of the semiconductor substrate using a thermal oxidation process.
Ion implantation may be employed to adjust threshold voltages of high-voltage PMOS and low-voltage NMOS/PMOS. A gate oxide layer for high-voltage or low-voltage elements may be formed, and a gate conductive layer is deposited and patterned to form the gate electrode.
A lightly doped drain (LDD) area may be formed in the low-voltage NMOS/PMOS by an ion implantation process. Also, a source/drain area may be formed in the high-voltage and low-voltage elements. Several post-processes including a process for forming a contact and a metal wiring layer may be executed.
FIG. 1 is an image of a semiconductor device obtained by an ESM (Electron scanning microscope). If an EDMOS (Extended Drain MOS) for use in a high-voltage element is manufactured by the LOCOS process, it may be difficult to control distance A, a thin voltage channel size B, and a well barrier D as shown in FIG. 1. The adjustment of a locos-fox thickness C may be considered to be a critical variable.
The most important aspect of the locos-fox thickness C may be to always maintain a constant thickness for a gate oxide layer. The reference character “B” indicates a channel size. All transistors may vary in channel size.
If the well-barrier size (D) is small, a well breakdown voltage may cause unexpected problems. If the well-barrier size (D) is large, short channels may be created since the distance “A” may become shorter. A bird beak phenomenon may occur due to the difficulties with adjusting the A, B, C, and D sizes, resulting in an increased channel size.